This invention relates to a termination structure, and more particularly relates to a termination structure for a DMOS device as well as a method for forming the same.
A diffused metal-oxide-semiconductor (DMOS) transistor is an important power transistor device and is widely used in power suppliers and power control devices for high-voltage systems. Among many published power transistor structures, a trenched power transistor is a noble design and some reports indicate that it has better performance than a planar power transistor in efficiency and pattern density.
A typical fabrication method for forming a trenched DMOS is shown in FIG. 1A through FIG. 1F. In FIG. 1A, an N-type epi layer 10 is formed on an N+-type silicon substrate 1, and then a thermal oxidation process is performed to form a termination oxide layer 20 over a location of a termination structure. The termination oxide layer 20 is utilized as a mask for a P-type doping to form a P-type active area 12. In FIG. 1B, the P-type active area 12 is etched to form a plurality of DMOS trenches 13 extending through the P-type body 12 down to the N-type epi layer 10. Afterward, an oxidation process is performed to form a gate oxide layer 21 over the active area 12 and also to grow the termination oxide layer 20 to become a field oxide layer 22. In FIG. 1C, a polysilicon layer is formed by a chemical vapor deposition (CVD) process and then etched to remove polysilicon on the surface of the epi layer 10 around the DMOS trenches 13. A polysilicon gate 30 then is formed in each DMOS trench. In FIG. 1D, a lithographic process is performed to define locations of source regions 40. Using a photoresist layer 40PR on the source regions 40, N-type dopants are implanted into the active area 12 to form N+-type source regions 40 surrounding the DMOS trenches 13. In FIG. 1E, an isolation layer 50 is formed by a CVD process. An etch is performed to form a plurality of body contact windows 51 over the N+-type source regions 40. Moreover, P-type dopants are implanted into the body contact windows to form doped regions 41 surrounding the source regions. In FIG. 1F, a source metal contact layer 60 is deposited over the isolation layer 50. The source metal contact layer 60 connects with the active area 12 through the body contact windows 51. The source metal contact layer 60 has contact windows to expose the isolation layer 50. In addition, a drain metal contact layer 61 covers the backside of the N-type silicon substrate 1. With a voltage applied on the polysilicon gate, it can show whether the source regions of the DMOS trenches are conductive to the drain regions.
A trenched power transistor performs better than a planar power transistor. However, the structure of a trenched power transistor is more complex than that of a planar power transistor. Therefore, reducing the number of lithographic process steps is one way of improving the manufacturing process.
For the abovementioned lithographic process, the process improvement focuses on canceling the lithographic steps for the source region implantation and polysilicon layer deposition. As shown in FIG. 2, N-type dopants are directly implanted without a mask (not shown) which is used for forming a source region photoresist 40PR and defining the scope of implantation of a source region 40 as a source region mask. The silicon substrate 1 is masked by the field oxide layer 22 and the polysilicon gates 30, so that a small gap is formed having the horizontal width w (marked as A) between the N-type doped area 40a and the N-type epi layer 10 on the P-type active area 12. Punch-through occurs easily in the location A on the P-type active area 12 and leads to breakdown of the transistor.
To avoid the effects of electrostatic discharge on power transistors, an ESD (Electrostatic Discharge) protective circuit 14 is usually utilized in the IC design. A typical ESD 14 is shown in FIG. 3. It is noted that, to form a polysilicon layer 32, a mask is needed to define the location of the ESD polysilicon layer 32. As a consequence, the lithographic process related to the polysilicon layer deposition cannot be neglected usually.
In addition, because the power transistor device is usually utilized under a higher electric voltage, a termination structure should be added thereto for avoiding early breakdown and current leakage. In the art, various structures such as a local oxidation of silicon (LOCOS), a field plate, a guard ring or the like can be utilized as the termination structure. In particular, the LOCOS structure is well known for its simple fabrication process.
In the typical trenched DMOS device as shown in FIG. 1B, the field oxide layer 22 is utilized as the main body of the termination structure. However, due to the process characteristics of the field oxide layer 22, the electric field crowding around the active area 12 is improved with limitation. The better result can be reached by combining some other termination structures such as a field plate, for example.
Referring to FIG. 4A, a typical field plate 16 is shown. The field plate is a conductive layer over the oxide layer, and is typically made of polysilicon or metal. When the field plate 16 is applied with a negative bias, positive charges are formed under the field plate 16 thereof so as to extend the boundary of the depletion region of P-N junction from 15 to 15′. On the other hand, when the field plate 16 is biased positively, to the boundary will move from 15 to 15″. In FIG. 4B, a planar P-N junction is shown, connected with an electric plate 16 and having a boundary 15 of the depletion region of the planar P-N junction. The electric field crowding effect near the junction surface 161 can be improved by applying a negative bias on the field plate 16.